1. Field of the Invention
The invention concerns memories made in integrated circuit form. It also concerns random-access memories (RAMs) as well as read-only memories (ROMs, EPROMs or EEPROMs). However, it is particularly valuable in the case of flash EPROMs which are electrically programmable and electrically erasable by blocks.
More precisely, the invention concerns the redundancy systems associated with these memories.
2. Description of the Prior Art
The French Patent Application 87/02372 filed on Feb. 24, 1987 and published as French Patent Application Publication No. 2,6111,301 on Aug. 26, 1988 describes a redundancy system aimed at optimizing the possibilities of repairing defective columns by means of a limited number of redundancy columns, when the memory is organized ion lines and columns with a number of columns that is a multiple of the number of data output pads of the memory. In other words, the memory is designed to give words of k bits (for example k=8) and there are k times p columns (for example p=64). The memory has k groups of p columns and the selection of a word in the memory is done by the simultaneous selection of a single column in each group. The text of the French Patent Application can be consulted for more details.
The redundancy system of the French Patent Application is based on the idea that the number of redundancy columns will be limited by memorizing not only the address of a defective column (1 among p) designed to be replaced by a redundancy column but also a position of the pad corresponding to the defective column.
The position of the pad is not necessarily the one having the rank 1 among k ranks of the pad. In the French Patent Application Publication, it is somewhat fictitious position chosen in the following way: k pads are arranged in m sets of r pads, and a redundant column or a group of redundant columns is associated with each set. The "pad position" is one position among r positions of the pad within the set to which it belongs. To give a numerical example, if there are eight pads (k=8) arranged in four sets (m=4) of two pads (r=2), there are two possible pad positions in each set, which could be called position 0 and position 1. When a defective column is detected and has to be replaced by a redundant column, not only is this defective column replaced by a redundant column, but also there is a simultaneous replacement of all the (non-defective) columns that correspond to the same pad position in the other sets and are selected by the same column address. Thus, in the numerical example given here above, if a defective column corresponding to a pad position 1 is identified, the putting into operation of the redundancy will consist in the replacement, by a respective redundant column, of the four position 1 columns which are selected by a defective column address. But columns having the same column address but with pad position 0 are not replaced.
This redundancy system is therefore based on the permanent memorizing of several pieces of information pertaining to the defective columns.
Firstly, addresses of defective columns are memorized, in a memory of defective column addresses. Each address makes it possible to designate one defective column among p in a group of p columns without distinction among the k groups. A comparator permanently monitors the addresses applied to the memory, in reading as well as in writing. If a defective column address appears, the comparator reacts by indicating that the redundancy must be put into operation. It also indicates the repair number that should be triggered when, as is generally the case, several possibilities of repairing are provided for, and are identified by numbers.
Then, for each repair number, the pad position corresponding to the actually defective column is memorized, without any distinction among the sets. This information is recorded in pad position memorizing elements. When a defective address appears at the input of the memory, it is identified by the comparator. The comparator determines the repair number that has to be put into operation, and gives a corresponding piece of information enabling the selection of the pad position memorizing elements which correspond to this number. The selected elements define a pad position. All the groups of columns that correspond to this position will undergo a replacement of a column (defective or not) by a redundant column.
In practice, in the prior patent application FR 87/02371, the pad position memorizing elements are fuses: if there are only two pad positions, one fuse alone will be enough to define this position. If there are four of them, two fuses will be needed, etc. These fuses will be needed for each repair number.
When there is only one pad position out of two to be defined, the practical construction is fairly simple: it is enough to have simple logic circuits to:
receive a piece of information on a repair number from the comparator; PA0 select the memorization element (the fuse) that corresponds to this number, as a function of this piece of information, PA0 and examine the state of the corresponding fuse, to set up an instruction for the selection of the pads for which the pad position is the one indicated by the fuse. PA0 firstly, select a group of fuses among N, if there are N possible repair numbers; PA0 secondly, designate the different pad positions corresponding to the state of the different fuses or transistors for a given repair number; PA0 and finally, record the state of the pad position memorizing elements, when the memory is tested. PA0 select the redundancy columns having a same position, this position being defined by the state of a group of three fuses; PA0 electrically record the state of the fuses on the basis of the result of the test showing that there is a defective column.
Although this situation is fairly simple, it should be pointed out all the same that it must take account of the need to record the information on pad position. In one approach using fuses, it can be imagined that the fuses will be blown out by laser, in which case no circuitry is needed for the recording. This is the approach adopted in the already-mentioned Patent Application 87/02372. However today, for reasons of automation, it is preferred to do an electrical recording. This enables the recording to be done immediately when the existence of defective columns is detected. For an electrical recording, the corresponding circuitry is needed. This is true for a memorizing operation using a fuse, but it is also true if the memorizing element is a floating gate transistor, now coming into increasing use as a permanent information memorizing element.
Where the situation gets extremely complicated is when the number of pad positions to be memorized increases along with the number of possibilities of repair. Indeed, in this case, a very fast complex decoding is needed to:
For example, if there are six possible repairs and eight pad positions, there should be six groups of three fuses or transistors, and a complex decoding to set up the connections that are suitable for choosing one group among six, and to:
In practice, the piece of information on pad position to be recorded electrically should come from somewhere. It will be seen that it comes from the pad on which a fault has been identified. This assumes, therefore, that pad position memorizing elements are connected in one way or another to the corresponding pads in order to do the recording.
All the connections, decoders and routings necessary make it fairly difficult to implement this principle of redundancy with memorization of the position of pads.
Besides, the difficulty does not lie solely in a circuit where the k pads are arranged in m sets of r pads with one pad position among r defined simultaneously for all the sets. It also exists in the borderline case where m=1, i.e. in the case where the pad position is one position among k in a single set of k pads.
The present invention proposes to resolve this difficulty by increasing the number of pad position memorizing elements in relation to what is strictly necessary, and by organizing these element in the form of a matrix of electrically programmable memory cells (floating gate transistors).
The access to the matrix is got linewise by conductors coming from the comparator (comparing the memory addresses received with the defective column addresses), each conductor corresponding to a repair number and to a respective line of the matrix; the output is done column wise towards read/write circuits associated with each column. Each read/write circuit corresponds to a pad position and, during the pad position recording stage, it receives a piece of information coming from a pad corresponding to this position.
Each column of the memory corresponds to a respective pad position. The appearance of a determined bit on this column corresponds to the selection of a determined pad position. It is thus that, on N lines, it is possible to memorize N different pad positions which are the positions corresponding to N different defective columns.
In one example with six possibilities of repair and eight pad positions, there will be 48 floating gate transistors organized in matrix form, while the standard construction would entail only 18 floating gate transistors. However, an enormous gain is obtained with respect to the corresponding decoding circuitry, moreover without complicating the programming operation: the programming will be done line by line (six lines), directly on the basis of a piece of information coming from a pad.